FIG. 1 shows a typical configuration for an integrated circuit including a flash EEPROM (electrically erasable and programmable ROM) memory array 100 and circuitry enabling programming, erasing, reading, and overerase correction for memory cells in the array 100. The flash EEPROM array 100 is composed of individual cells, such as cell 102. Each cell has a drain connected to a bit line, such as bit line 104, each bit line being connected to a bit line switch circuit 106 and column decoder 108. Sources of the array cells are connected to each other and VSL, which is the common source signal, while their gates are each connected by a word line to a row decoder 110.
The row decoder 110 receives voltage signals from a power supply 112 and distributes the particular voltage signals to the word lines as controlled by a row address received from a processor or state machine 114. Likewise, the bit line switch circuit 106 receives voltage signals from the power supply 112 and distributes the particular voltage signals to the bit lines as controlled by a signal from the processor 114. Voltages provided by the power supply 112 are controlled by signals received from processor 114.
The column decoder 108 provides signals from particular bit lines to sense amplifiers or comparators 116 as controlled by a column address signal received from processor 114. The power supply 112 supplies voltages to column decoder 108 and bit lines 104. Power supply 112 may include a charge pump circuit or external power supply to supply the bit line current on a bit line needed during programming or overerase correction.
The sense amplifiers 116 receive a signal from reference cells of reference array 118. With signals from the column decoder 108 and reference array 118, the sense amplifiers 116 then each provide a signal indicating a state of a bit line relative to a reference cell line to which it is connected through data latches or buffers 120 to processor 114.
To program a cell in the flash memory array 100, high gate-to-source voltage pulses are provided to the cell from power supply 112 while a source of the cell is grounded. For instance, during programming multiple gate voltage pulses typically of 9-10 V are each applied for approximately three to six microseconds to a cell, while a drain voltage of the cell is set to 4-4.5 V and its source is grounded. This bias from-drain to-source generates hot electrons near the drain side. The large gate-to-source voltage pulses enable a probability of hot electrons to overcome an energy barrier between the channel and floating gate formed by a thin dielectric layer, thereby driving hot electrons onto the floating gate of the cell. This programming procedure, termed “hot electron injection” results in an increase of a threshold voltage for the cell, the threshold being the gate-to-source voltage required for the cell to conduct.
After an erase operation, there is concern with what is known in the art as “overerase.” An overerased cell has a threshold voltage that is too low and provides leakage current even when the gate-to-source voltage is at 0V. The cell leakage will form a non-negligible bit line current, which leads to reading and programming errors. Therefore, overerase correction is performed to reduce this bit line current. During overerase correction, all of the cells on a bit line in the flash memory array 100 have the same gate-to-source voltage with the source grounded. The drain voltage of the cell is set to around 5V. Again, hot electrons will be injected into the floating gate to raise the threshold voltages of the cells.
During the program operation, a program-verify step is performed by applying a gate voltage of 6V to the control gate electrode of the main cell, a drain voltage of 1V to the drain, a gate voltage of 3V to the control gate electrode of a reference cell and a drain voltage of 1V to the drain.
The entire program operation is repeatedly performed for all of the memory cells in a pre-selected unit, for example for the memory cells in a word unit (i.e., 16 bits). More specifically, the program and the program-verify steps are first performed for all corresponding memory cells included in the word unit. Next, it is determined whether failed memory cells exist within the word unit. If it is determined that failed cells exist, the program step and the program-verify step are performed for the failed cells. These processes are performed until failed memory cells do not exist.
Generally, when that the program operation is performed in the word unit, the program current flowing from the drain to the source is very high. Therefore, in some prior art programming operations, the program operation is internally performed in byte units in order to increase the program efficiency and to reduce the operating current of the drain pump. In other words, the program step is first performed for the I/O (input/output)<7:0> (i.e., 8 bits) and the program step is then performed for a next I/O<15:8> (i.e., 8 bits). Next, the program-verify step is performed for the entire word unit I/O<15:0> (i.e., 16 bits). If any failed cells are detected, the above processes are repeated. If no failed cells are detected, the program operation is finished.
If the program operation is repeatedly performed, a program pulse is always applied twice for every 8 bits even though there exist passed bits among the 16 cells. In other words, assuming that the program time is 5 μs per byte, the program time is increased by an integer times every time when the failed cells occur, e.g., 5 μs×2=10 μs per byte. This stresses the charge pump that provides the bias for the program operation and also increases the total time for the program operation. Further, the retention capability of the cells can be degraded due to over-programming since the bias is repeatedly applied to already-programmed cells.
U.S. Pat. No. 6,751,158 to Ryoo describes a programming method for programming word units that seeks to address some of these concerns. A bit counter counts the total number of bits from the selected word unit that are to be programmed. If the number of bits of the data to be programmed is less than eight, the program operation is performed on the entire word, rather than splitting the word into byte units for individual programming. If the total number of bits of data to be programmed is greater than eight, the word unit is programmed as two individual byte units. The operation of the Ryoo device is predicated on the assumption that for bit counts larger than eight, the supplied programming current cannot be enough for the required bits to be programmed. Thus, the sixteen bits, which includes both bits to be programmed and those that are not to be programmed, are divided into two groups, e.g., high byte and low byte, for individual programming. Based on Ryoo's assumption, each byte will necessarily include eight or fewer bits for programming and thus the supply current will be sufficient.
The general allowable operating range for a given memory device is, for example, 2.7 to 3.6V. One problem with Ryoo's methodology is that the prediction of inadequate programming current for more than eight bits does not hold true for high VCC operating voltages (e.g., 3.6 V). Pumping current is usually much larger for high VCC voltages than for low VCC voltages (e.g., 2.7 V). Ryoo's methodology applies affords the same longer program time for each VCC environment though unnecessary for the high VCC environment. Therefore, in high VCC environments, Ryoo's methodology results in wasted programming time.
Therefore, there remains a need for a semiconductor memory device with improved programming capabilities and efficiencies.